ekko/LPT26x-HSF-4MB-Hilink_14.2.0.308_20250411
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

添加bootload相关代码，以及配置。支持pwm在bootload开启

Browse Source
This commit is contained in:
Ekko.bao
2025-07-03 23:54:38 +08:00
parent e600ac3f22
commit 289bce290c
6 changed files with 1532 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -2,7 +2,6 @@
*.so
*.bin
output
bootloader
libs_url
open_source
temp

55
bootloader/flashboot_ws63/CMakeLists.txt Executable file
View File

@ -0,0 +1,55 @@
#===============================================================================
# @brief cmake file
# Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2022. All rights reserved.
#===============================================================================
set(COMPONENT_NAME "flashboot_common")
if("flashboot" IN_LIST BIN_NAME)
set(SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/startup/main.c
${CMAKE_CURRENT_SOURCE_DIR}/startup/main.c
${CMAKE_CURRENT_SOURCE_DIR}/startup/riscv_init.S
${CMAKE_CURRENT_SOURCE_DIR}/../commonboot/src/secure_verify_boot.c
)
set(PUBLIC_HEADER
${CMAKE_CURRENT_SOURCE_DIR}/include
${CMAKE_CURRENT_SOURCE_DIR}/../commonboot/include
)
elseif ("ssb" IN_LIST BIN_NAME)
set(SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/ssb/main.c
${CMAKE_CURRENT_SOURCE_DIR}/ssb/riscv_init.S
${CMAKE_CURRENT_SOURCE_DIR}/../commonboot/src/secure_verify_boot.c
)
set(PUBLIC_HEADER
${CMAKE_CURRENT_SOURCE_DIR}/../commonboot/include
)
endif()
set(PRIVATE_HEADER
)
set(PRIVATE_DEFINES
)
set(PUBLIC_DEFINES
)
# use this when you want to add ccflags like -include xxx
set(COMPONENT_PUBLIC_CCFLAGS
)
set(COMPONENT_CCFLAGS
)
set(WHOLE_LINK
true
)
set(MAIN_COMPONENT
false
)
build_component()

1203
bootloader/flashboot_ws63/startup/main.c Executable file
View File

File diff suppressed because it is too large Load Diff

93
bootloader/flashboot_ws63/startup/riscv_init.S Executable file
View File

@ -0,0 +1,93 @@
/*
* Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2021-2021. All rights reserved.
* Description: main
*
* Create: 2021-03-09
*/
.section .text.entry
.global _start
.option norvc
_start:
j Reset_Handler
Reset_Handler:
li t0,0x0
csrw pmpcfg0,t0
li t0,0x0
csrw pmpcfg1,t0
li t0,0x0
csrw pmpcfg2,t0
li t0,0x0
csrw pmpcfg3,t0
li t0,0x0
csrw 0x7d9,t0
la t0, __flash_boot_flag_begin__
mv t1, a0
lw t3, (t1)
sw t3, (t0)
la t0, trap_vector
addi t0, t0, 1
csrw mtvec, t0
csrwi mstatus, 0
csrwi mie, 0
# initialize global pointer
la gp, _gp_
# initialize stack pointer
la sp, __stack_top__
/* init stack */
la t0, g_system_stack_begin
la t1, g_system_stack_end
beq t0, t1, end_set_stack_loop
li t2, 0xefbeadde
set_stack_loop:
sw t2, (t0)
addi t0, t0, 4
blt t0, t1, set_stack_loop
end_set_stack_loop:
/* clear reg */
li ra, 0
li tp, 0
li s0, 0
li s1, 0
li a0, 0
li a1, 0
li a2, 0
li a3, 0
li a4, 0
li a5, 0
li a6, 0
li a7, 0
li s2, 0
li s3, 0
li s4, 0
li s5, 0
li s6, 0
li s7, 0
li s8, 0
li s9, 0
li s10, 0
li s11, 0
li t3, 0
li t4, 0
li t5, 0
li t6, 0
/* clear bss section */
la t0, __bss_begin__
la t1, __bss_end__
beq t0, t1, end_clear_bss_loop
li t2, 0x00000000
clear_bss_loop:
sw t2, (t0)
addi t0, t0, 4
blt t0, t1, clear_bss_loop
end_clear_bss_loop:
j start_fastboot

BIN
build/config/target_config/ws63/fota/__pycache__/fota_format_st.cpython-39.pyc
View File

Binary file not shown.

181
drivers/chips/ws63/porting/pwm/pwm_porting.c Executable file
View File

@ -0,0 +1,181 @@
/**
* Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2022. All rights reserved.
*
* Description: Provides pwm port \n
*
* History: \n
* 2022-09-16， Create file. \n
*/
#include "chip_core_irq.h"
#include "soc_osal.h"
#include "common_def.h"
#include "hal_pwm_v151.h"
#include "platform_core.h"
#include "chip_io.h"
#include "soc_porting.h"
#include "pwm_porting.h"
#define BUS_CLOCK_TIME_40M 40000000UL
#define BIT_WIDTH_LIMIT 0xFFFF
#define CLDO_CRG_CLK_SEL 0x44001134
#define PWM_CKSEL_BIT 7
#define CLDO_SUB_CRG_CKEN_CTL0 0x44001100
#define CLDO_CRG_DIV_CTL3 0x44001114
#define CLDO_CRG_DIV_CTL4 0x44001118
#define CLDO_CRG_DIV_CTL5 0x4400111C
#define PWM_BUS_CKEN 2
#define PWM_CHANNEL_CKEN_LEN 9
#define PWM0_LOAD_DIV_EN 20
#define PWM0_DIV1_CFG 16
#define PWM0_DIV1_CFG_LEN 4
#define PWM1_LOAD_DIV_EN 30
#define PWM1_DIV1_CFG 26
#define PWM1_DIV1_CFG_LEN 4
#define PWM2_LOAD_DIV_EN 8
#define PWM2_DIV1_CFG 4
#define PWM2_DIV1_CFG_LEN 4
#define PWM3_LOAD_DIV_EN 18
#define PWM3_DIV1_CFG 14
#define PWM3_DIV1_CFG_LEN 4
#define PWM4_LOAD_DIV_EN 28
#define PWM4_DIV1_CFG 24
#define PWM4_DIV1_CFG_LEN 4
#define PWM5_LOAD_DIV_EN 8
#define PWM5_DIV1_CFG 4
#define PWM5_DIV1_CFG_LEN 4
#define PWM6_LOAD_DIV_EN 18
#define PWM6_DIV1_CFG 14
#define PWM6_DIV1_CFG_LEN 4
#define PWM7_LOAD_DIV_EN 28
#define PWM7_DIV1_CFG 24
#define PWM7_DIV1_CFG_LEN 4
#define PWM_DIV_6 6
#define PWM_DIV_10 10
uintptr_t g_pwm_base_addr = (uintptr_t)PWM_0_BASE;
uintptr_t pwm_porting_base_addr_get(void)
{
return g_pwm_base_addr;
}
static int pwm_handler(int a, const void *tmp)
{
unused(a);
unused(tmp);
hal_pwm_v151_irq_handler();
return 0;
}
void pwm_port_register_hal_funcs(void)
{
hal_pwm_register_funcs(hal_pwm_v151_funcs_get());
}
void pwm_port_unregister_hal_funcs(void)
{
hal_pwm_unregister_funcs();
}
void pwm_port_clock_enable(bool on)
{
if (on == true) {
uint32_t div_cfg = PWM_DIV_6;
#ifdef CONFIG_HIGH_FREQUENCY
uapi_reg_setbit(CLDO_CRG_CLK_SEL, PWM_CKSEL_BIT);
#elif defined(CONFIG_LOW_FREQUENCY)
uapi_reg_clrbit(CLDO_CRG_CLK_SEL, PWM_CKSEL_BIT);
if (get_tcxo_freq() == CLK24M_TCXO) {
div_cfg = PWM_DIV_6;
} else {
div_cfg = PWM_DIV_10;
}
#endif
reg32_setbits(CLDO_SUB_CRG_CKEN_CTL0, PWM_BUS_CKEN, PWM_CHANNEL_CKEN_LEN, 0x1FF);
reg32_clrbit(CLDO_CRG_DIV_CTL3, PWM0_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL3, PWM0_DIV1_CFG, PWM0_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL3, PWM0_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL3, PWM1_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL3, PWM1_DIV1_CFG, PWM1_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL3, PWM1_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL4, PWM2_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL4, PWM2_DIV1_CFG, PWM2_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL4, PWM2_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL4, PWM3_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL4, PWM3_DIV1_CFG, PWM3_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL4, PWM3_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL4, PWM4_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL4, PWM4_DIV1_CFG, PWM4_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL4, PWM4_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL5, PWM5_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL5, PWM5_DIV1_CFG, PWM5_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL5, PWM5_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL5, PWM6_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL5, PWM6_DIV1_CFG, PWM6_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL5, PWM6_LOAD_DIV_EN);
reg32_clrbit(CLDO_CRG_DIV_CTL5, PWM7_LOAD_DIV_EN);
reg32_setbits(CLDO_CRG_DIV_CTL5, PWM7_DIV1_CFG, PWM7_DIV1_CFG_LEN, div_cfg);
reg32_setbit(CLDO_CRG_DIV_CTL5, PWM7_LOAD_DIV_EN);
} else {
reg32_clrbits(CLDO_SUB_CRG_CKEN_CTL0, PWM_BUS_CKEN, PWM_CHANNEL_CKEN_LEN);
}
}
void pwm_port_register_irq(pwm_channel_t channel)
{
unused(channel);
osal_irq_request((uintptr_t)PWM_ABNOR_IRQN, (osal_irq_handler)pwm_handler, NULL, NULL, NULL);
osal_irq_enable((uintptr_t)PWM_ABNOR_IRQN);
}
void pwm_port_unregister_irq(pwm_channel_t channel)
{
unused(channel);
#ifndef BUILD_NOOSAL
osal_irq_disable((uintptr_t)PWM_ABNOR_IRQN);
osal_irq_disable((uintptr_t)PWM_CFG_IRQN);
osal_irq_free((uintptr_t)PWM_ABNOR_IRQN, NULL);
osal_irq_free((uintptr_t)PWM_CFG_IRQN, NULL);
#endif
}
void pwm_irq_lock(uint8_t channel)
{
unused(channel);
osal_irq_lock();
}
void pwm_irq_unlock(uint8_t channel)
{
unused(channel);
osal_irq_unlock();
}
uint32_t pwm_port_get_clock_value(pwm_channel_t channel)
{
if (channel >= PWM_MAX_NUMBER) {
return 0;
}
return BUS_CLOCK_TIME_40M;
}
errcode_t pwm_port_param_check(const pwm_config_t *cfg)
{
if ((cfg->low_time + cfg->high_time > BIT_WIDTH_LIMIT) || (cfg->offset_time > cfg->low_time)) {
return ERRCODE_PWM_INVALID_PARAMETER;
}
return ERRCODE_SUCC;
}