187 lines
6.3 KiB
C
187 lines
6.3 KiB
C
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/**
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* Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2023-2023. All rights reserved.
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*
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* Description: SPI Sample Source. \n
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*
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* History: \n
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* 2023-06-25, Create file. \n
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*/
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#include "pinctrl.h"
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#include "spi.h"
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#include "soc_osal.h"
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#include "app_init.h"
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#define SPI_SLAVE_NUM 1
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#define SPI_FREQUENCY 2
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#define SPI_CLK_POLARITY 0
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#define SPI_CLK_PHASE 0
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#define SPI_FRAME_FORMAT 0
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#define SPI_FRAME_FORMAT_STANDARD 0
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#define SPI_FRAME_SIZE_8 0x1f
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#define SPI_TMOD 0
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#define SPI_WAIT_CYCLES 0x10
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#if defined(CONFIG_SPI_SUPPORT_DMA) && !(defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH))
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#define SPI_DMA_WIDTH 2
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#endif
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#if defined(CONFIG_SPI_MASTER_SUPPORT_QSPI)
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#define QSPI_WRITE_CMD 0x38
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#define QSPI_WRITE_ADDR 0x123
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#endif
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#define SPI_TASK_DURATION_MS 500
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#define SPI_TASK_PRIO 24
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#define SPI_TASK_STACK_SIZE 0x1000
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static void app_spi_init_pin(void)
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{
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uapi_pin_set_mode(CONFIG_SPI_DI_MASTER_PIN, CONFIG_SPI_MASTER_PIN_MODE);
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uapi_pin_set_mode(CONFIG_SPI_DO_MASTER_PIN, CONFIG_SPI_MASTER_PIN_MODE);
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uapi_pin_set_mode(CONFIG_SPI_CLK_MASTER_PIN, CONFIG_SPI_MASTER_PIN_MODE);
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uapi_pin_set_mode(CONFIG_SPI_CS_MASTER_PIN, CONFIG_SPI_MASTER_PIN_MODE);
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#if defined(CONFIG_SPI_MASTER_SUPPORT_QSPI)
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uapi_pin_set_mode(CONFIG_SPI_MASTER_D2_PIN, CONFIG_SPI_MASTER_D2_PIN_MODE);
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uapi_pin_set_mode(CONFIG_SPI_MASTER_D3_PIN, CONFIG_SPI_MASTER_D3_PIN_MODE);
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#endif
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}
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#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
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static void app_spi_master_write_int_handler(const void *buffer, uint32_t length)
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{
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unused(buffer);
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unused(length);
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osal_printk("spi master write interrupt start!\r\n");
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}
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static void app_spi_master_rx_callback(const void *buffer, uint32_t length, bool error)
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{
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if (buffer == NULL || length == 0) {
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osal_printk("spi master transfer illegal data!\r\n");
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return;
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}
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if (error) {
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osal_printk("app_spi_master_read_int error!\r\n");
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return;
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}
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uint8_t *buff = (uint8_t *)buffer;
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for (uint32_t i = 0; i < length; i++) {
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osal_printk("buff[%d] = %x\r\n", i, buff[i]);
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}
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osal_printk("app_spi_master_read_int success!\r\n");
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}
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#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
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static void app_spi_master_init_config(void)
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{
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spi_attr_t config = { 0 };
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spi_extra_attr_t ext_config = { 0 };
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config.is_slave = false;
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config.slave_num = SPI_SLAVE_NUM;
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config.bus_clk = SPI_CLK_FREQ;
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config.freq_mhz = SPI_FREQUENCY;
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config.clk_polarity = SPI_CLK_POLARITY;
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config.clk_phase = SPI_CLK_PHASE;
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config.frame_format = SPI_FRAME_FORMAT;
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config.spi_frame_format = HAL_SPI_FRAME_FORMAT_STANDARD;
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config.frame_size = SPI_FRAME_SIZE_8;
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config.tmod = SPI_TMOD;
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config.sste = 0;
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ext_config.qspi_param.wait_cycles = SPI_WAIT_CYCLES;
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#if defined(CONFIG_SPI_MASTER_SUPPORT_QSPI)
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config.tmod = HAL_SPI_TRANS_MODE_TX;
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config.sste = 0;
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config.spi_frame_format = HAL_SPI_FRAME_FORMAT_QUAD;
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ext_config.qspi_param.trans_type = HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q;
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ext_config.qspi_param.inst_len = HAL_SPI_INST_LEN_8;
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ext_config.qspi_param.addr_len = HAL_SPI_ADDR_LEN_24;
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ext_config.qspi_param.wait_cycles = 0;
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#endif
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uapi_spi_init(CONFIG_SPI_MASTER_BUS_ID, &config, &ext_config);
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#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
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uapi_dma_init();
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uapi_dma_open();
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#ifndef CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH
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spi_dma_config_t dma_cfg = {
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.src_width = SPI_DMA_WIDTH,
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.dest_width = SPI_DMA_WIDTH,
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.burst_length = 0,
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.priority = 0
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};
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if (uapi_spi_set_dma_mode(CONFIG_SPI_MASTER_BUS_ID, true, &dma_cfg) != ERRCODE_SUCC) {
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osal_printk("spi%d master set dma mode fail!\r\n");
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}
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#endif
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#endif /* CONFIG_SPI_SUPPORT_DMA */
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#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
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if (uapi_spi_set_irq_mode(CONFIG_SPI_MASTER_BUS_ID, true, app_spi_master_rx_callback,
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app_spi_master_write_int_handler) == ERRCODE_SUCC) {
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osal_printk("spi%d master set irq mode succ!\r\n", CONFIG_SPI_MASTER_BUS_ID);
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}
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#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
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}
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static void *spi_master_task(const char *arg)
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{
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unused(arg);
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/* SPI pinmux. */
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app_spi_init_pin();
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/* SPI master init config. */
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app_spi_master_init_config();
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/* SPI data config. */
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uint8_t tx_data[CONFIG_SPI_TRANSFER_LEN] = { 0 };
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for (uint32_t loop = 0; loop < CONFIG_SPI_TRANSFER_LEN; loop++) {
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tx_data[loop] = (loop & 0xFF);
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}
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uint8_t rx_data[CONFIG_SPI_TRANSFER_LEN] = { 0 };
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spi_xfer_data_t data = {
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.tx_buff = tx_data,
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.tx_bytes = CONFIG_SPI_TRANSFER_LEN,
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.rx_buff = rx_data,
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.rx_bytes = CONFIG_SPI_TRANSFER_LEN,
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#if defined(CONFIG_SPI_MASTER_SUPPORT_QSPI)
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.cmd = QSPI_WRITE_CMD,
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.addr = QSPI_WRITE_ADDR,
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#endif
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};
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while (1) {
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osal_msleep(SPI_TASK_DURATION_MS);
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osal_printk("spi%d master send start!\r\n", CONFIG_SPI_MASTER_BUS_ID);
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if (uapi_spi_master_write(CONFIG_SPI_MASTER_BUS_ID, &data, 0xFFFFFFFF) == ERRCODE_SUCC) {
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osal_printk("spi%d master send succ!\r\n", CONFIG_SPI_MASTER_BUS_ID);
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} else {
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continue;
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}
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osal_printk("spi%d master receive start!\r\n", CONFIG_SPI_MASTER_BUS_ID);
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if (uapi_spi_master_read(CONFIG_SPI_MASTER_BUS_ID, &data, 0xFFFFFFFF) == ERRCODE_SUCC) {
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#ifndef CONFIG_SPI_SUPPORT_INTERRUPT
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for (uint32_t i = 0; i < data.rx_bytes; i++) {
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osal_printk("spi%d master receive data is %x\r\n", CONFIG_SPI_MASTER_BUS_ID, data.rx_buff[i]);
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}
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#endif
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osal_printk("spi%d master receive succ!\r\n", CONFIG_SPI_MASTER_BUS_ID);
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}
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}
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return NULL;
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}
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static void spi_master_entry(void)
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{
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osal_task *task_handle = NULL;
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osal_kthread_lock();
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task_handle = osal_kthread_create((osal_kthread_handler)spi_master_task, 0, "SpiMasterTask", SPI_TASK_STACK_SIZE);
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if (task_handle != NULL) {
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osal_kthread_set_priority(task_handle, SPI_TASK_PRIO);
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osal_kfree(task_handle);
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}
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osal_kthread_unlock();
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}
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/* Run the spi_master_entry. */
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app_run(spi_master_entry);
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